Events

Powering AI: The Semiconductor Ecosystem at the Foundation of Data Centers

Date:
June 2, 2026

Time:
1:00-2:00 pm ET

 

Semiconductors are the building blocks of Artificial Intelligence (AI).  

The Semiconductor Industry Association invites you to a high-level briefing on the complex semiconductor ecosystem that makes AI possible. We will examine the hardware components, forecast the market, and discuss the technical challenges that industry leaders face as they create the next generation of AI hardware. 

A single AI server rack relies on approximately 4,500 individual chips working in perfect harmony to power today’s massive AI workloads. Understanding this intricate ecosystem is critical for anyone looking to navigate the future of technology and AI infrastructure. 

Webinar Agenda & Highlights 

  1. Keynote Address: Component Mapping & Market Forecast 
  • Presented by: Duncan Stewart, Deloitte 
  • We will kick off with a 15-minute keynote providing an exclusive overview of our latest report’s component mapping. This session will highlight essential market forecasts and high-level content value analyses for AI hardware. 
  1. Industry Presentations: Deep Dive with 6 Leading Semiconductor Companies 

Following the keynote, the webinar will shift to a series of technical presentations from six pioneering semiconductor firms. Each company will examine its unique product mix and discuss the engineering bottlenecks they are overcoming within the AI data center segment. 

The presentations will cover four critical pillars: 

  • Intel, Compute: The processing power driving complex model training and inference. 
  • Infineon, Global Foundries, Texas Instruments, Foundational Products: The power, signal, and thermal management components needed to enable compute and ensure rack-level stability. 
  •  Arm, Cadence, Value Chain: The design, manufacturing, and packaging supply chains required to deliver these components to the market. As well as a look at data center operational considerations. 

What You’ll Learn 

  • Current market forecasts and financial valuation of AI data center components. 
  • The taxonomy of the 4,500 semiconductor devices underpinning the modern AI rack. 
  • The immediate technical challenges industry participants must solve to create next-generation AI hardware. 

Who Should Attend? 

  • Semiconductor Policy Makers 
  • Industry Analysts, Investors, and Market Strategists tracking the AI hardware boom 
  • Data Center Architects and Hardware Engineers 
  • Supply Chain Professionals 

Can’t attend? Register to receive the post-event recording. 

Please click below to view the slides from the webinar:

Presentations

 

Date:

June 2, 2026

 

 

Keynote:

Duncan Stewart 
Managing Director of Global Semiconductor Research & Managing Director of Global Telecom Research
Deloitte 

Duncan has co-authored Deloitte’s TMT Predictions, since 2008. With 36 years of experience in the TMT industry, Duncan provides insight about what’s going to happen next – a key strategic driver for companies in all industries. Duncan is the Managing Director of global semiconductor research and the Managing Director of global telecom research for the US TMT Center and for Deloitte Global, and speaks to 100s of TMT clients around the world annually 

 

Panelists: 

Bahaa Fahim
Intel Fellow: Xeon Chief Engineer 
Intel
 

Bahaa is Xeon Chief Engineer in Intel’s Data Center Group. He leads technical definition and execution Xeon products focused on high quality end-to-end SoC functional execution in the areas of micro-architecture, logic design, validation, and post-silicon, from initial product concept through production. Bahaa is responsible for driving new innovations and transformation concepts to enable improved performance, cost efficiency, scalability, and quality for high priority Xeon and custom Xeon products for Intel.  

Bahaa joined Intel in 2001 and is based in Santa Clara. He has a master’s degree in electrical engineering from Stanford University and a bachelor’s degree in computer engineering from Purdue University. He holds 35 issued patents and two Intel achievement awards and is a regular participant in Industry forums. 

 

Athar Zaidi
Senior Vice President and General Manager of Power ICs and Connectivity Systems 
Infineon
 

Athar Zaidi is an accomplished technology executive with hands-on experience in developing and marketing engineering solutions. He is currently Senior Vice President and General Manager of Infineon’s Power ICs and Connectivity Systems Business Line in the Power & Sensor Systems Division, and oversees (AI) server, Datacom, Telecom, high end consumer, charger & adapter, power tools, consumer electronics, mobile and PC products.

 

Thomas Barber
Vice President of Communications Infrastructure and Data Center 
GlobalFoundries
 

Thomas Barber is the Vice President of Communications Infrastructure and Data Center at GlobalFoundries, where he leads the teams defining strategy for high-speed optical connectivity across advanced semiconductor technologies, silicon photonics, and advanced packaging. He brings extensive experience working with hyperscalers, telecommunications and optical module vendors to deliver scalable solutions for AI and cloud data centers. Thomas is actively engaged in shaping next‑generation interconnect architectures, with a particular focus on pluggable and co‑packaged optical transceivers. 

Mr. Barber has a master’s degree in Electrical Engineering from MIT and an MBA from Northeastern University.

 

Satadal Bhattacharjee 
Global Head of Cloud and AI Infrastructure Silicon
Arm

Satadal Bhattacharjee is a seasoned technology and product executive with more than 25 years of experience driving innovation across AI, cloud computing, mobility, and infrastructure. He has held leadership roles at Uber, AWS, Qualcomm, and Broadcom, building and scaling products that serve global markets. His expertise spans product strategy, business development, data centers, AI platforms, and emerging technologies. Satadal is also an active advisor, investor, and mentor, known for connecting deep technical insight with strong business execution.

 

Sherman Ikemoto
Group Director 
Cadence
 

Sherman Ikemoto is a Group Director at Cadence where he leads business development for the innovative Reality DC Digital Twin solution. With a passion for addressing challenges in data center design, performance, and sustainability, Sherman brings extensive expertise to the forefront of this critical industry. Previously, Sherman served as Managing Director and Board Member at Future Facilities, the pioneer of the original data center Digital Twin, and as Sales and Marketing Director at Flomerics, where he helped introduce computational fluid dynamics modeling to electronics cooling design. Sherman is a sought-after speaker at prominent industry events such as ITW, Data Center World, Uptime Symposium, and Data Center Dynamics. Sherman holds a BSME from San Jose State University and an MSME from Santa Clara University. 

 

Robert Taylor
General Manager, Power Design Services
Texas Instruments

Robert Taylor is a Sector General Manager at Texas Instruments Inc. responsible for Power Design Services. He has over 20 years of power supply design experience with a focus on solving customer design challenges. His focus is on supporting rapidly growing markets through the development of reference designs and innovative customer driven solutions. Robert is a Senior Member of Technical Staff at TI and is a proud graduate of the University of Florida (BSEE 2002, MSEE 2004).

 

Moderated By:

Erik Hadland
Director of Technology Policy
Semiconductor Industry Association

Erik Hadland is the Director of Technology Policy at the Semiconductor Industry Association (SIA), where he is responsible for the association’s research, development, and technology activities as well as its education and workforce development efforts. In this role, he works with the White House, Federal agencies, and Congress to inform policymakers about the needs and functions of the diverse segments of the semiconductor industry.

Prior to SIA, Erik was a AAAS Science and Technology Policy Fellow at the U.S. Department of Energy, where he served as Advisor to the Director of the Office of Science—the Nation’s largest supporter of fundamental physical science research and stewarding office of 10 of the Department’s National Laboratories. In this capacity, Erik project managed briefings to the Congress on critical and emergent technologies, advised on matters of place-based innovation and technology transfer, and co-facilitated the Department’s Microelectronics Working Group. Prior to the DOE, Erik was a Senior Logic Technology Development Engineer at Intel, piloting first-of-a-kind annealing modules and processing conditions for Intel’s next generation logic products.

Erik earned his PhD in Solid State Chemistry from the University of Oregon, where he studied novel synthesis schemes for metastable 2D semiconductor compounds.

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